14
Available Options
AV-51001
2013.12.26
Available Options
Figure 5: Sample Ordering Code and Available Options for Arria V ST Devices
Embedded Hard IPs
M : 1 hard PCIe controller and
2 hard memory controllers
F : 2 hard PCIe controllers and
3 hard memory controllers
Transceiver Count
Maximum channels
E : 12
G : 18
K : 30
Package Type
F : FineLine BGA (FBGA)
Operating Temperature
I : Industrial (T J = -40° C to 100° C)
Family Signature
5A
ST
F
D5
K
3
F
40
I
3
N
5A : Arria V
Family Variant
Optional Suffix
Indicates specific device
Package Code 5
ST :   SoC with 10-Gbps transceivers
Member Code
D3 : 350K logic elements
D5 : 462K logic elements
Transceiver
Speed Grade
3 : 10.3125 Gbps
31 : 896 pins
options or shipment method
FPGA Fabric
Speed Grade N : Lead-free packaging
Contact Altera for availability
3 (fastest)
of leaded options
ES : Engineering sample
35 : 1,152 pins
40 : 1,517 pins
Maximum Resources
Table 12: Maximum Resource Counts for Arria V ST Devices
Resource
Logic Elements (LE) (K)
ALM
Register
D3
350
132,075
528,300
Member Code
D5
462
174,340
697,360
Memory (Kb)
Variable-precision DSP Block
18 x 18 Multiplier
FPGA PLL
HPS PLL
Transceiver
FPGA GPIO (10)
M10K
MLAB
6-Gbps
10-Gbps (9)
17,290
2,014
809
1,618
14
3
30
16
540
22,820
2,658
1,090
2,180
14
3
30
16
540
(9)
(10)
Chip-to-chip connections only. For 10 Gbps channel usage conditions, refer to the Transceiver Architecture
in Arria V Devices chapter.
The number of GPIOs does not include transceiver I/Os. In the Quartus II software, the number of user I/Os
includes transceiver I/Os.
Altera Corporation
Arria V Device Overview
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